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[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5670d 13h /dbg_interface/tags/rel_21/rtl/verilog
134 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7492d 15h /dbg_interface/tags/rel_21/rtl/verilog
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7536d 22h /dbg_interface/tags/rel_21/rtl/verilog
123 All flipflops are reset. mohor 7541d 19h /dbg_interface/tags/rel_21/rtl/verilog
121 Port signals are all set to zero after reset. mohor 7544d 19h /dbg_interface/tags/rel_21/rtl/verilog
119 cpu_stall_o activated as soon as bp occurs. mohor 7544d 22h /dbg_interface/tags/rel_21/rtl/verilog
117 Define name changed. mohor 7546d 18h /dbg_interface/tags/rel_21/rtl/verilog
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7548d 01h /dbg_interface/tags/rel_21/rtl/verilog
106 Sensitivity list updated. simons 7548d 23h /dbg_interface/tags/rel_21/rtl/verilog
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7549d 14h /dbg_interface/tags/rel_21/rtl/verilog
102 New version. mohor 7549d 15h /dbg_interface/tags/rel_21/rtl/verilog
101 Almost finished. mohor 7549d 16h /dbg_interface/tags/rel_21/rtl/verilog
100 *** empty log message *** mohor 7550d 18h /dbg_interface/tags/rel_21/rtl/verilog
99 cpu registers added. mohor 7550d 18h /dbg_interface/tags/rel_21/rtl/verilog
97 Working. mohor 7551d 20h /dbg_interface/tags/rel_21/rtl/verilog
95 Temp version. mohor 7552d 10h /dbg_interface/tags/rel_21/rtl/verilog
94 temp version. Resets will be changed in next version. mohor 7552d 20h /dbg_interface/tags/rel_21/rtl/verilog
93 tmp version. mohor 7553d 21h /dbg_interface/tags/rel_21/rtl/verilog
92 temp version. mohor 7557d 01h /dbg_interface/tags/rel_21/rtl/verilog
91 tmp version. mohor 7557d 20h /dbg_interface/tags/rel_21/rtl/verilog

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