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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rev_23/] - Rev 121

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Rev	Log message	Author	Age	Path
121	Port signals are all set to zero after reset.	mohor	7510d 05h	/dbg_interface/tags/rev_23
120	test stall_test added.	mohor	7510d 08h	/dbg_interface/tags/rev_23
119	cpu_stall_o activated as soon as bp occurs.	mohor	7510d 09h	/dbg_interface/tags/rev_23
117	Define name changed.	mohor	7512d 05h	/dbg_interface/tags/rev_23
116	Data latching changed when testing WB.	mohor	7512d 05h	/dbg_interface/tags/rev_23
115	More debug data added.	mohor	7512d 09h	/dbg_interface/tags/rev_23
114	CRC generation iand verification in bench changed.	mohor	7512d 10h	/dbg_interface/tags/rev_23
113	IDCODE test improved.	mohor	7512d 11h	/dbg_interface/tags/rev_23
112	dbg_tb_defines.v not used.	mohor	7513d 06h	/dbg_interface/tags/rev_23
111	Define tap_defines.v added to test bench.	mohor	7513d 06h	/dbg_interface/tags/rev_23
110	Waiting for "ready" improved.	mohor	7513d 07h	/dbg_interface/tags/rev_23
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7513d 12h	/dbg_interface/tags/rev_23
106	Sensitivity list updated.	simons	7514d 10h	/dbg_interface/tags/rev_23
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7515d 01h	/dbg_interface/tags/rev_23
102	New version.	mohor	7515d 01h	/dbg_interface/tags/rev_23
101	Almost finished.	mohor	7515d 02h	/dbg_interface/tags/rev_23
100	* empty log message *	mohor	7516d 04h	/dbg_interface/tags/rev_23
99	cpu registers added.	mohor	7516d 04h	/dbg_interface/tags/rev_23
97	Working.	mohor	7517d 07h	/dbg_interface/tags/rev_23
96	Working.	mohor	7517d 08h	/dbg_interface/tags/rev_23

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[/] [dbg_interface/] [tags/] [rev_23/] - Rev 121

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