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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] - Rev 141

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Rev Log message Author Age Path
141 data_cnt_lim length changed to reduce number of warnings. igorm 7413d 03h /dbg_interface/trunk/rtl/verilog
139 New release of the debug interface (3rd. release). igorm 7415d 21h /dbg_interface/trunk/rtl/verilog
138 Temp version before changing dbg interface. igorm 7422d 01h /dbg_interface/trunk/rtl/verilog
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7474d 07h /dbg_interface/trunk/rtl/verilog
123 All flipflops are reset. mohor 7479d 03h /dbg_interface/trunk/rtl/verilog
121 Port signals are all set to zero after reset. mohor 7482d 03h /dbg_interface/trunk/rtl/verilog
119 cpu_stall_o activated as soon as bp occurs. mohor 7482d 07h /dbg_interface/trunk/rtl/verilog
117 Define name changed. mohor 7484d 03h /dbg_interface/trunk/rtl/verilog
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7485d 10h /dbg_interface/trunk/rtl/verilog
106 Sensitivity list updated. simons 7486d 08h /dbg_interface/trunk/rtl/verilog
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7486d 23h /dbg_interface/trunk/rtl/verilog
102 New version. mohor 7486d 23h /dbg_interface/trunk/rtl/verilog
101 Almost finished. mohor 7487d 00h /dbg_interface/trunk/rtl/verilog
100 *** empty log message *** mohor 7488d 03h /dbg_interface/trunk/rtl/verilog
99 cpu registers added. mohor 7488d 03h /dbg_interface/trunk/rtl/verilog
97 Working. mohor 7489d 05h /dbg_interface/trunk/rtl/verilog
95 Temp version. mohor 7489d 18h /dbg_interface/trunk/rtl/verilog
94 temp version. Resets will be changed in next version. mohor 7490d 05h /dbg_interface/trunk/rtl/verilog
93 tmp version. mohor 7491d 06h /dbg_interface/trunk/rtl/verilog
92 temp version. mohor 7494d 10h /dbg_interface/trunk/rtl/verilog

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