OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [tags/] [eco32-0.23] - Rev 87

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
87 disk: master boot made compatible with monitor hellwig 3785d 05h /eco32/tags/eco32-0.23
86 disk: master boot made compatible with monitor hellwig 3785d 20h /eco32/tags/eco32-0.23
85 monitor: bootstrap parameters modified hellwig 3786d 04h /eco32/tags/eco32-0.23
84 monitor: bad address register added hellwig 3786d 11h /eco32/tags/eco32-0.23
83 simulator: individual help messages hellwig 3787d 00h /eco32/tags/eco32-0.23
82 simulator: change command @ -> #, better help for commands hellwig 3787d 01h /eco32/tags/eco32-0.23
81 hardware: cpu now has a bad address register hellwig 3787d 10h /eco32/tags/eco32-0.23
80 hwtests/xcptest now tests the bad address register too hellwig 3787d 11h /eco32/tags/eco32-0.23
79 hwtests (kbd): second timer added hellwig 3788d 02h /eco32/tags/eco32-0.23
78 simulator: tlbBadAddr register is now called mmuBadAddr hellwig 3789d 05h /eco32/tags/eco32-0.23
77 hardware: ucf file re-formatted hellwig 3790d 08h /eco32/tags/eco32-0.23
76 AUTHORS update hellwig 3790d 23h /eco32/tags/eco32-0.23
75 hardware: cpu now equal to port-15 hellwig 3790d 23h /eco32/tags/eco32-0.23
74 when simulating the system include a console hellwig 3791d 04h /eco32/tags/eco32-0.23
73 use xess monitor when simulating the system hellwig 3791d 05h /eco32/tags/eco32-0.23
72 simulator: IRQ 0-3 explanation changed hellwig 3791d 07h /eco32/tags/eco32-0.23
71 simulator: IRQ 15 explanation added hellwig 3791d 08h /eco32/tags/eco32-0.23
70 hardware: two timers hellwig 3792d 00h /eco32/tags/eco32-0.23
69 hardware: timer counts clock cycles, counter is readable hellwig 3792d 03h /eco32/tags/eco32-0.23
68 hardware: timer now equal to port-15 hellwig 3792d 06h /eco32/tags/eco32-0.23

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.