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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 363

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Rev Log message Author Age Path
363 quartus project files unneback 4736d 06h /ethmac/branches/unneback/rtl/verilog
362 added Makefiles to build project unneback 4736d 07h /ethmac/branches/unneback/rtl/verilog
361 created branch unneback unneback 4736d 07h /ethmac/branches/unneback/rtl/verilog
352 Removed delayed assignments from rtl code olof 4747d 08h /ethmac/branches/unneback/rtl/verilog
351 Turn defines into parameters in eth_cop olof 4755d 22h /ethmac/branches/unneback/rtl/verilog
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4755d 23h /ethmac/branches/unneback/rtl/verilog
349 Make all parameters configurable from top level olof 4756d 23h /ethmac/branches/unneback/rtl/verilog
346 Updated project location olof 4758d 01h /ethmac/branches/unneback/rtl/verilog
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4768d 01h /ethmac/branches/unneback/rtl/verilog
338 root 5562d 03h /ethmac/branches/unneback/rtl/verilog
335 New directory structure. root 5619d 08h /ethmac/branches/unneback/rtl/verilog
333 Some small fixes + some troubles fixed. igorm 7067d 22h /ethmac/branches/unneback/rtl/verilog
332 Case statement improved for synthesys. igorm 7081d 04h /ethmac/branches/unneback/rtl/verilog
330 Warning fixes. igorm 7096d 06h /ethmac/branches/unneback/rtl/verilog
329 Defer indication fixed. igorm 7096d 07h /ethmac/branches/unneback/rtl/verilog
328 Delayed CRC fixed. igorm 7096d 07h /ethmac/branches/unneback/rtl/verilog
327 Defer indication fixed. igorm 7096d 07h /ethmac/branches/unneback/rtl/verilog
326 Delayed CRC fixed. igorm 7096d 08h /ethmac/branches/unneback/rtl/verilog
325 Defer indication fixed. igorm 7096d 08h /ethmac/branches/unneback/rtl/verilog
323 Accidently deleted line put back. igorm 7393d 08h /ethmac/branches/unneback/rtl/verilog

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