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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 352

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Rev	Log message	Author	Age	Path
352	Removed delayed assignments from rtl code	olof	4692d 22h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
346	Updated project location	olof	4703d 15h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
338		root	5507d 17h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
335	New directory structure.	root	5564d 22h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
333	Some small fixes + some troubles fixed.	igorm	7013d 12h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
325	Defer indication fixed.	igorm	7041d 21h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
276	Defer indication changed.	tadejm	7794d 19h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7864d 06h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7872d 10h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7934d 17h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
146	CarrierSenseLost status is not set when working in loopback mode.	mohor	7942d 14h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
126	InvalidSymbol generation changed.	mohor	7983d 14h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8077d 18h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
70	Small fixes.	mohor	8140d 21h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8143d 15h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
43	Tx status is written back to the BD.	mohor	8147d 23h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
42	Rx status is written back to the BD.	mohor	8150d 16h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
37	Link in the header changed.	mohor	8166d 22h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8262d 23h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
18	Few little NCSIM warnings fixed.	mohor	8300d 18h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 352

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