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[/] [ethmac/] [tags/] [rel_10/] - Rev 96

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Rev Log message Author Age Path
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8125d 00h /ethmac/tags/rel_10
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8125d 03h /ethmac/tags/rel_10
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 8125d 03h /ethmac/tags/rel_10
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8130d 01h /ethmac/tags/rel_10
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8131d 04h /ethmac/tags/rel_10
91 Comments in Slovene language removed. mohor 8131d 04h /ethmac/tags/rel_10
90 casex changed with case, fifo reset changed. mohor 8131d 04h /ethmac/tags/rel_10
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.		 mohor 8135d 02h /ethmac/tags/rel_10
88 rx_fifo was not always cleared ok. Fixed. mohor 8141d 01h /ethmac/tags/rel_10
87 Status was not latched correctly sometimes. Fixed. mohor 8141d 03h /ethmac/tags/rel_10
86 Big Endian problem when sending frames fixed. mohor 8142d 10h /ethmac/tags/rel_10
85 Log info was missing. mohor 8147d 20h /ethmac/tags/rel_10
84 LinkFail signal was not latching appropriate bit. mohor 8147d 20h /ethmac/tags/rel_10
83 MAC address recognition was not correct (bytes swaped). mohor 8147d 20h /ethmac/tags/rel_10
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8147d 21h /ethmac/tags/rel_10
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8147d 22h /ethmac/tags/rel_10
80 Small fixes for external/internal DMA missmatches. mohor 8152d 00h /ethmac/tags/rel_10
79 RetryCntLatched was unused and removed from design mohor 8152d 00h /ethmac/tags/rel_10
78 WB_SEL_I was unused and removed from design mohor 8152d 00h /ethmac/tags/rel_10
77 Interrupts changed mohor 8152d 00h /ethmac/tags/rel_10

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