OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [bench/] [verilog] - Rev 194

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
194 Full duplex tests modified and testbench bug repaired. tadej 7953d 15h /ethmac/tags/rel_14/bench/verilog
192 Some additional reports added tadej 7955d 12h /ethmac/tags/rel_14/bench/verilog
191 Bug repaired in eth_phy device tadej 7955d 12h /ethmac/tags/rel_14/bench/verilog
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7955d 13h /ethmac/tags/rel_14/bench/verilog
188 PHY changed. tadej 7956d 09h /ethmac/tags/rel_14/bench/verilog
182 Full duplex test improved. tadej 7957d 12h /ethmac/tags/rel_14/bench/verilog
181 MIIM test look better. mohor 7957d 14h /ethmac/tags/rel_14/bench/verilog
180 Bench outputs data to display every 128 bytes. mohor 7960d 10h /ethmac/tags/rel_14/bench/verilog
179 Beautiful tests merget together mohor 7960d 11h /ethmac/tags/rel_14/bench/verilog
178 Rearanged testcases mohor 7960d 11h /ethmac/tags/rel_14/bench/verilog
177 Bug in MIIM fixed. mohor 7960d 15h /ethmac/tags/rel_14/bench/verilog
170 Headers changed. mohor 7960d 17h /ethmac/tags/rel_14/bench/verilog
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7960d 18h /ethmac/tags/rel_14/bench/verilog
158 Typo fixed. mohor 7965d 13h /ethmac/tags/rel_14/bench/verilog
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7967d 18h /ethmac/tags/rel_14/bench/verilog
156 Valid testbench. mohor 7967d 19h /ethmac/tags/rel_14/bench/verilog
155 Minor changes. mohor 7967d 19h /ethmac/tags/rel_14/bench/verilog
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8010d 12h /ethmac/tags/rel_14/bench/verilog
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8012d 13h /ethmac/tags/rel_14/bench/verilog
117 Clock mrx_clk set to 2.5 MHz. mohor 8016d 16h /ethmac/tags/rel_14/bench/verilog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.