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[/] [ethmac/] [tags/] [rel_17/] - Rev 221

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7911d 14h /ethmac/tags/rel_17
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7914d 15h /ethmac/tags/rel_17
218 Typo error fixed. (When using Bist) mohor 7914d 17h /ethmac/tags/rel_17
217 Bist supported. mohor 7914d 17h /ethmac/tags/rel_17
216 Bist signals added. mohor 7914d 17h /ethmac/tags/rel_17
215 Bist supported. mohor 7914d 18h /ethmac/tags/rel_17
214 Signals for WISHBONE B3 compliant interface added. mohor 7915d 14h /ethmac/tags/rel_17
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7915d 14h /ethmac/tags/rel_17
212 Minor $display change. mohor 7915d 14h /ethmac/tags/rel_17
211 Bist added. mohor 7915d 14h /ethmac/tags/rel_17
210 BIST added. mohor 7915d 14h /ethmac/tags/rel_17
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7916d 17h /ethmac/tags/rel_17
208 Virtual Silicon RAMs moved to lib directory tadej 7932d 11h /ethmac/tags/rel_17
207 Virtual Silicon RAM support fixed tadej 7932d 11h /ethmac/tags/rel_17
206 Virtual Silicon RAM added to the simulation. mohor 7932d 11h /ethmac/tags/rel_17
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7932d 12h /ethmac/tags/rel_17
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7932d 12h /ethmac/tags/rel_17
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7932d 12h /ethmac/tags/rel_17
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7935d 13h /ethmac/tags/rel_17
201 Core size added to the document. mohor 7935d 14h /ethmac/tags/rel_17

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