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[/] [ethmac/] [tags/] [rel_18/] - Rev 87

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Rev Log message Author Age Path
87 Status was not latched correctly sometimes. Fixed. mohor 8145d 03h /ethmac/tags/rel_18
86 Big Endian problem when sending frames fixed. mohor 8146d 10h /ethmac/tags/rel_18
85 Log info was missing. mohor 8151d 19h /ethmac/tags/rel_18
84 LinkFail signal was not latching appropriate bit. mohor 8151d 19h /ethmac/tags/rel_18
83 MAC address recognition was not correct (bytes swaped). mohor 8151d 19h /ethmac/tags/rel_18
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8151d 21h /ethmac/tags/rel_18
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8151d 22h /ethmac/tags/rel_18
80 Small fixes for external/internal DMA missmatches. mohor 8155d 23h /ethmac/tags/rel_18
79 RetryCntLatched was unused and removed from design mohor 8156d 00h /ethmac/tags/rel_18
78 WB_SEL_I was unused and removed from design mohor 8156d 00h /ethmac/tags/rel_18
77 Interrupts changed mohor 8156d 00h /ethmac/tags/rel_18
76 Interrupts changed in the top file mohor 8156d 00h /ethmac/tags/rel_18
75 r_Bro is used for accepting/denying frames mohor 8156d 00h /ethmac/tags/rel_18
74 Reset values are passed to registers through parameters mohor 8156d 00h /ethmac/tags/rel_18
73 Number of interrupts changed mohor 8156d 00h /ethmac/tags/rel_18
72 Retry is not activated when a Tx Underrun occured mohor 8160d 04h /ethmac/tags/rel_18
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.
mohor 8164d 05h /ethmac/tags/rel_18
70 Small fixes. mohor 8164d 06h /ethmac/tags/rel_18
69 Define missmatch fixed. mohor 8165d 03h /ethmac/tags/rel_18
68 Registered trimmed. Unused registers removed. mohor 8166d 02h /ethmac/tags/rel_18

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