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Rev Log message Author Age Path
245 Rev 1.7. mohor 7904d 03h /ethmac/tags/rel_19
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7904d 05h /ethmac/tags/rel_19
243 Late collision is not reported any more. tadejm 7904d 11h /ethmac/tags/rel_19
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7905d 02h /ethmac/tags/rel_19
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7905d 02h /ethmac/tags/rel_19
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7905d 02h /ethmac/tags/rel_19
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7905d 02h /ethmac/tags/rel_19
238 Defines fixed to use generic RAM by default. mohor 7917d 06h /ethmac/tags/rel_19
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7919d 11h /ethmac/tags/rel_19
235 rev 4. mohor 7920d 02h /ethmac/tags/rel_19
234 Figure list assed to the revision 3. mohor 7920d 10h /ethmac/tags/rel_19
233 Revision 0.3 released. Some figures added. mohor 7920d 10h /ethmac/tags/rel_19
232 fpga define added. mohor 7925d 05h /ethmac/tags/rel_19
231 Description of Core Modules added (figure). mohor 7927d 07h /ethmac/tags/rel_19
229 case changed to casex. mohor 7931d 03h /ethmac/tags/rel_19
227 Changed BIST scan signals. tadejm 7931d 07h /ethmac/tags/rel_19
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7931d 08h /ethmac/tags/rel_19
225 Some minor changes. tadejm 7931d 09h /ethmac/tags/rel_19
224 Signals for a wave window in Modelsim. tadejm 7931d 10h /ethmac/tags/rel_19
223 Some code changed due to bug fixes. tadejm 7931d 10h /ethmac/tags/rel_19

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