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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 106

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Rev	Log message	Author	Age	Path
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8065d 23h	/ethmac/tags/rel_19/rtl/verilog
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8075d 00h	/ethmac/tags/rel_19/rtl/verilog
104	FCS should not be included in NibbleMinFl.	mohor	8076d 18h	/ethmac/tags/rel_19/rtl/verilog
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8076d 19h	/ethmac/tags/rel_19/rtl/verilog
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8076d 19h	/ethmac/tags/rel_19/rtl/verilog
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8076d 19h	/ethmac/tags/rel_19/rtl/verilog
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8076d 19h	/ethmac/tags/rel_19/rtl/verilog
97	Small typo fixed.	lampret	8100d 17h	/ethmac/tags/rel_19/rtl/verilog
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8104d 17h	/ethmac/tags/rel_19/rtl/verilog
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8104d 20h	/ethmac/tags/rel_19/rtl/verilog
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8104d 20h	/ethmac/tags/rel_19/rtl/verilog
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8109d 18h	/ethmac/tags/rel_19/rtl/verilog
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8110d 20h	/ethmac/tags/rel_19/rtl/verilog
91	Comments in Slovene language removed.	mohor	8110d 20h	/ethmac/tags/rel_19/rtl/verilog
90	casex changed with case, fifo reset changed.	mohor	8110d 20h	/ethmac/tags/rel_19/rtl/verilog
88	rx_fifo was not always cleared ok. Fixed.	mohor	8120d 17h	/ethmac/tags/rel_19/rtl/verilog
87	Status was not latched correctly sometimes. Fixed.	mohor	8120d 19h	/ethmac/tags/rel_19/rtl/verilog
86	Big Endian problem when sending frames fixed.	mohor	8122d 02h	/ethmac/tags/rel_19/rtl/verilog
85	Log info was missing.	mohor	8127d 12h	/ethmac/tags/rel_19/rtl/verilog
84	LinkFail signal was not latching appropriate bit.	mohor	8127d 12h	/ethmac/tags/rel_19/rtl/verilog

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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 106

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