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[/] [ethmac/] [tags/] [rel_23/] [bench/] [verilog/] - Rev 267

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Rev Log message Author Age Path
267 Full duplex control frames tested. mohor 7853d 04h /ethmac/tags/rel_23/bench/verilog
266 Flow control test almost finished. mohor 7858d 03h /ethmac/tags/rel_23/bench/verilog
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7858d 18h /ethmac/tags/rel_23/bench/verilog
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7859d 07h /ethmac/tags/rel_23/bench/verilog
254 Temp version. mohor 7861d 00h /ethmac/tags/rel_23/bench/verilog
252 Just some updates. tadejm 7861d 03h /ethmac/tags/rel_23/bench/verilog
243 Late collision is not reported any more. tadejm 7866d 07h /ethmac/tags/rel_23/bench/verilog
227 Changed BIST scan signals. tadejm 7893d 04h /ethmac/tags/rel_23/bench/verilog
223 Some code changed due to bug fixes. tadejm 7893d 07h /ethmac/tags/rel_23/bench/verilog
216 Bist signals added. mohor 7900d 07h /ethmac/tags/rel_23/bench/verilog
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7902d 07h /ethmac/tags/rel_23/bench/verilog
194 Full duplex tests modified and testbench bug repaired. tadej 7921d 06h /ethmac/tags/rel_23/bench/verilog
192 Some additional reports added tadej 7923d 03h /ethmac/tags/rel_23/bench/verilog
191 Bug repaired in eth_phy device tadej 7923d 03h /ethmac/tags/rel_23/bench/verilog
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7923d 04h /ethmac/tags/rel_23/bench/verilog
188 PHY changed. tadej 7924d 01h /ethmac/tags/rel_23/bench/verilog
182 Full duplex test improved. tadej 7925d 03h /ethmac/tags/rel_23/bench/verilog
181 MIIM test look better. mohor 7925d 06h /ethmac/tags/rel_23/bench/verilog
180 Bench outputs data to display every 128 bytes. mohor 7928d 01h /ethmac/tags/rel_23/bench/verilog
179 Beautiful tests merget together mohor 7928d 02h /ethmac/tags/rel_23/bench/verilog

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