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[/] [ethmac/] [tags/] [rel_6/] - Rev 117

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Rev Log message Author Age Path
117 Clock mrx_clk set to 2.5 MHz. mohor 7995d 03h /ethmac/tags/rel_6
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7995d 03h /ethmac/tags/rel_6
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7996d 01h /ethmac/tags/rel_6
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7996d 22h /ethmac/tags/rel_6
113 RxPointer bug fixed. mohor 8003d 14h /ethmac/tags/rel_6
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8004d 04h /ethmac/tags/rel_6
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8004d 17h /ethmac/tags/rel_6
110 m_wb_cyc_o signal released after every single transfer. mohor 8004d 20h /ethmac/tags/rel_6
109 Comment removed. mohor 8004d 21h /ethmac/tags/rel_6
108 Testbench supports unaligned accesses. mohor 8072d 06h /ethmac/tags/rel_6
107 TX_BUF_BASE changed. mohor 8072d 06h /ethmac/tags/rel_6
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8072d 07h /ethmac/tags/rel_6
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8081d 08h /ethmac/tags/rel_6
104 FCS should not be included in NibbleMinFl. mohor 8083d 02h /ethmac/tags/rel_6
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8083d 03h /ethmac/tags/rel_6
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8083d 03h /ethmac/tags/rel_6
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8083d 03h /ethmac/tags/rel_6
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8083d 03h /ethmac/tags/rel_6
99 Document revised. mohor 8090d 02h /ethmac/tags/rel_6
98 Document revised. mohor 8090d 02h /ethmac/tags/rel_6

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