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[/] [ethmac/] [tags/] [rel_6/] - Rev 121

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Rev Log message Author Age Path
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7980d 17h /ethmac/tags/rel_6
120 Unused files removed. mohor 7980d 18h /ethmac/tags/rel_6
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7980d 18h /ethmac/tags/rel_6
118 ShiftEnded synchronization changed. mohor 7984d 09h /ethmac/tags/rel_6
117 Clock mrx_clk set to 2.5 MHz. mohor 7984d 20h /ethmac/tags/rel_6
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7984d 20h /ethmac/tags/rel_6
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7985d 18h /ethmac/tags/rel_6
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7986d 15h /ethmac/tags/rel_6
113 RxPointer bug fixed. mohor 7993d 07h /ethmac/tags/rel_6
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7993d 21h /ethmac/tags/rel_6
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7994d 10h /ethmac/tags/rel_6
110 m_wb_cyc_o signal released after every single transfer. mohor 7994d 13h /ethmac/tags/rel_6
109 Comment removed. mohor 7994d 14h /ethmac/tags/rel_6
108 Testbench supports unaligned accesses. mohor 8062d 00h /ethmac/tags/rel_6
107 TX_BUF_BASE changed. mohor 8062d 00h /ethmac/tags/rel_6
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8062d 00h /ethmac/tags/rel_6
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8071d 01h /ethmac/tags/rel_6
104 FCS should not be included in NibbleMinFl. mohor 8072d 19h /ethmac/tags/rel_6
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8072d 20h /ethmac/tags/rel_6
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8072d 20h /ethmac/tags/rel_6

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