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[/] [ethmac/] [tags/] [rel_7/] - Rev 126

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Rev Log message Author Age Path
126 InvalidSymbol generation changed. mohor 8006d 07h /ethmac/tags/rel_7
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 8006d 07h /ethmac/tags/rel_7
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8006d 08h /ethmac/tags/rel_7
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8008d 09h /ethmac/tags/rel_7
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8008d 09h /ethmac/tags/rel_7
120 Unused files removed. mohor 8008d 10h /ethmac/tags/rel_7
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8008d 10h /ethmac/tags/rel_7
118 ShiftEnded synchronization changed. mohor 8012d 01h /ethmac/tags/rel_7
117 Clock mrx_clk set to 2.5 MHz. mohor 8012d 12h /ethmac/tags/rel_7
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8012d 12h /ethmac/tags/rel_7
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8013d 09h /ethmac/tags/rel_7
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8014d 07h /ethmac/tags/rel_7
113 RxPointer bug fixed. mohor 8020d 23h /ethmac/tags/rel_7
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8021d 12h /ethmac/tags/rel_7
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8022d 02h /ethmac/tags/rel_7
110 m_wb_cyc_o signal released after every single transfer. mohor 8022d 05h /ethmac/tags/rel_7
109 Comment removed. mohor 8022d 05h /ethmac/tags/rel_7
108 Testbench supports unaligned accesses. mohor 8089d 15h /ethmac/tags/rel_7
107 TX_BUF_BASE changed. mohor 8089d 15h /ethmac/tags/rel_7
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8089d 15h /ethmac/tags/rel_7

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