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[/] [ethmac/] [trunk/] - Rev 127

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Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7986d 17h /ethmac/trunk
126 InvalidSymbol generation changed. mohor 7986d 18h /ethmac/trunk
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7986d 18h /ethmac/trunk
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7986d 19h /ethmac/trunk
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7988d 19h /ethmac/trunk
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7988d 19h /ethmac/trunk
120 Unused files removed. mohor 7988d 20h /ethmac/trunk
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7988d 20h /ethmac/trunk
118 ShiftEnded synchronization changed. mohor 7992d 11h /ethmac/trunk
117 Clock mrx_clk set to 2.5 MHz. mohor 7992d 22h /ethmac/trunk
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7992d 22h /ethmac/trunk
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7993d 20h /ethmac/trunk
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7994d 17h /ethmac/trunk
113 RxPointer bug fixed. mohor 8001d 09h /ethmac/trunk
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8001d 23h /ethmac/trunk
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8002d 12h /ethmac/trunk
110 m_wb_cyc_o signal released after every single transfer. mohor 8002d 15h /ethmac/trunk
109 Comment removed. mohor 8002d 16h /ethmac/trunk
108 Testbench supports unaligned accesses. mohor 8070d 01h /ethmac/trunk
107 TX_BUF_BASE changed. mohor 8070d 01h /ethmac/trunk

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