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[/] [ethmac10g/] [tags/] [V10/] - Rev 23

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23 First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations. godzilla 6741d 06h /ethmac10g/tags/V10
22 First cut. Original code from Easic but add some extra controls. godzilla 6741d 06h /ethmac10g/tags/V10
21 First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats.
So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.
godzilla 6741d 06h /ethmac10g/tags/V10
20 First cut. Still need to update the document with design changes. godzilla 6741d 06h /ethmac10g/tags/V10
19 First cut. godzilla 6741d 06h /ethmac10g/tags/V10
18 works well fisher5090 6745d 20h /ethmac10g/tags/V10
17 crc test fisher5090 6746d 02h /ethmac10g/tags/V10
16 use counter fisher5090 6749d 11h /ethmac10g/tags/V10
15 crc module fisher5090 6749d 11h /ethmac10g/tags/V10
14 no more used fisher5090 6749d 11h /ethmac10g/tags/V10
13 first commit. not yet ready to compile mvpratt 6749d 11h /ethmac10g/tags/V10
12 200MHZ fisher5090 6750d 20h /ethmac10g/tags/V10
11 200MHZ fisher5090 6750d 20h /ethmac10g/tags/V10
10 200MHZ fisher5090 6750d 20h /ethmac10g/tags/V10
9 with max frequence of 200MHZ fisher5090 6756d 15h /ethmac10g/tags/V10
8 achieve 111M fisher5090 6758d 17h /ethmac10g/tags/V10
7 passed post-map simulate fisher5090 6760d 00h /ethmac10g/tags/V10
6 removed files fisher5090 6762d 13h /ethmac10g/tags/V10
5 receive engine initial codes fisher5090 6762d 13h /ethmac10g/tags/V10
4 no message fisher5090 6762d 16h /ethmac10g/tags/V10

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