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[/] [ethmac10g/] [tags/] [V10/] - Rev 40

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40 This commit was manufactured by cvs2svn to create tag 'V10'. 6603d 08h /ethmac10g/tags/V10
39 first version fisher5090 6603d 08h /ethmac10g/tags/V10
38 deleted fisher5090 6603d 09h /ethmac10g/tags/V10
37 no message fisher5090 6603d 09h /ethmac10g/tags/V10
36 no message godzilla 6666d 17h /ethmac10g/tags/V10
35 no message godzilla 6669d 17h /ethmac10g/tags/V10
34 Rewritten code. godzilla 6669d 17h /ethmac10g/tags/V10
33 Rewritten code. godzilla 6669d 17h /ethmac10g/tags/V10
32 no message fisher5090 6687d 01h /ethmac10g/tags/V10
31 no message fisher5090 6687d 01h /ethmac10g/tags/V10
30 no message fisher5090 6715d 00h /ethmac10g/tags/V10
29 no message fisher5090 6715d 10h /ethmac10g/tags/V10
28 First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST. mvpratt 6717d 20h /ethmac10g/tags/V10
27 xilinx coregen fisher5090 6728d 01h /ethmac10g/tags/V10
26 good edition fisher5090 6728d 01h /ethmac10g/tags/V10
25 no message fisher5090 6728d 01h /ethmac10g/tags/V10
24 First cut. One of the main culprits for the timing violations. godzilla 6730d 16h /ethmac10g/tags/V10
23 First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations. godzilla 6730d 16h /ethmac10g/tags/V10
22 First cut. Original code from Easic but add some extra controls. godzilla 6730d 16h /ethmac10g/tags/V10
21 First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats.
So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.		 godzilla 6730d 16h /ethmac10g/tags/V10

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