OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] - Rev 28

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 *** empty log message *** rherveille 7966d 19h /i2c/tags/asyst_3
27 Cleaned up code rherveille 7966d 19h /i2c/tags/asyst_3
26 *** empty log message *** rherveille 7970d 03h /i2c/tags/asyst_3
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7998d 00h /i2c/tags/asyst_3
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7998d 00h /i2c/tags/asyst_3
23 *** empty log message *** rherveille 8125d 05h /i2c/tags/asyst_3
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8135d 10h /i2c/tags/asyst_3
21 no message rherveille 8221d 11h /i2c/tags/asyst_3
20 Added Appendix A rherveille 8221d 11h /i2c/tags/asyst_3
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8225d 07h /i2c/tags/asyst_3
18 no message rherveille 8252d 03h /i2c/tags/asyst_3
17 C-include file.
Initial release		 rherveille 8340d 08h /i2c/tags/asyst_3
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8352d 07h /i2c/tags/asyst_3
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8357d 06h /i2c/tags/asyst_3
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8357d 06h /i2c/tags/asyst_3
13 Fixed some synthesis warnings. rherveille 8368d 10h /i2c/tags/asyst_3
12 no message rherveille 8374d 01h /i2c/tags/asyst_3
11 Changed RST_LVL define to parameter. rherveille 8377d 09h /i2c/tags/asyst_3
10 Created new directory structure.
Added Verilog version.		 rherveille 8399d 05h /i2c/tags/asyst_3
9 Created directory structure (documentation, vhdl, verilog) rherveille 8469d 00h /i2c/tags/asyst_3

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.