OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] - Rev 42

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7588d 20h /i2c/tags/asyst_3
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7588d 20h /i2c/tags/asyst_3
39 Forgot an 'end if' :-/ rherveille 7608d 15h /i2c/tags/asyst_3
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7611d 23h /i2c/tags/asyst_3
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7648d 15h /i2c/tags/asyst_3
36 Fixed cmd_ack generation item (no bug). rherveille 7763d 16h /i2c/tags/asyst_3
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7797d 06h /i2c/tags/asyst_3
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7801d 04h /i2c/tags/asyst_3
33 Fixed a bug in the Command Register declaration. rherveille 7823d 13h /i2c/tags/asyst_3
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7833d 13h /i2c/tags/asyst_3
31 Core is now a Multimaster I2C controller. rherveille 7837d 14h /i2c/tags/asyst_3
30 Small code simplifications rherveille 7837d 14h /i2c/tags/asyst_3
29 Core is now a Multimaster I2C controller rherveille 7837d 15h /i2c/tags/asyst_3
28 *** empty log message *** rherveille 7863d 08h /i2c/tags/asyst_3
27 Cleaned up code rherveille 7863d 08h /i2c/tags/asyst_3
26 *** empty log message *** rherveille 7866d 16h /i2c/tags/asyst_3
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7894d 12h /i2c/tags/asyst_3
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7894d 12h /i2c/tags/asyst_3
23 *** empty log message *** rherveille 8021d 17h /i2c/tags/asyst_3
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8031d 22h /i2c/tags/asyst_3

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.