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Rev Log message Author Age Path
69 Updated simulation scripts
Obsolete sim script removed
ja_rd 4891d 17h /ion
68 Updated pre-generated vhdl files ja_rd 4891d 17h /ion
67 Deprecated files:
Marked three files as unused, to be removed
ja_rd 4891d 17h /ion
66 Code samples:
Updated all code samples to use TB2 template and new memory map
ja_rd 4891d 17h /ion
65 Fixed io input mux in MPU template 1 ja_rd 4891d 17h /ion
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)
ja_rd 4891d 17h /ion
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display
ja_rd 4891d 17h /ion
62 CPU fixed:
fixed bug in EPC load logic relative to mem_wait stalls
parametrized reset and trap vector addresses
ja_rd 4891d 17h /ion
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing
ja_rd 4891d 17h /ion
60 Forgot to upload new TB package!!
Without this, simulations don't work...
ja_rd 4891d 18h /ion
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file
ja_rd 4893d 07h /ion
58 Cleaned up cache stub code ja_rd 4893d 18h /ion
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit
ja_rd 4893d 19h /ion
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly
ja_rd 4893d 19h /ion
55 First version of cache: stub, 1-word cache
(forgot to commit new mpu template file)
ja_rd 4893d 20h /ion
54 Doc updated
Cache section (2.7) is still missing
ja_rd 4893d 23h /ion
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.
ja_rd 4893d 23h /ion
52 Sim scripts adapted to recent changes ja_rd 4893d 23h /ion
51 Adapted simulation and synth templates for cache module ja_rd 4893d 23h /ion
50 New code sample: memtest
Tests external RAM
ja_rd 4893d 23h /ion

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