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[/] [ion/] [trunk/] - Rev 161

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Rev Log message Author Age Path
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)		 ja_rd 4777d 15h /ion/trunk
160 BUG FIX: the cache init code was messing the BSS initialization ja_rd 4778d 17h /ion/trunk
159 bug detected but not fixed in cpu
(1st instruction after entering user mode is executed in kernel mode)		 ja_rd 4779d 00h /ion/trunk
158 removed file from TB directory which was committed by mistake ja_rd 4779d 00h /ion/trunk
157 Bug fix in the missing coprocesor exception.
The CPU was triggering a privilege exception for the mtc0 that went into user mode.
Logging HDL updated		 ja_rd 4780d 10h /ion/trunk
156 project doc somewhat updated (but still out of date) ja_rd 4780d 17h /ion/trunk
155 Temporary warning added to outdated project doc file ja_rd 4780d 18h /ion/trunk
154 fixed log trigger address in hello makefile ja_rd 4780d 19h /ion/trunk
153 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4780d 19h /ion/trunk
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4780d 19h /ion/trunk
151 BUG FIX: major bugs fixed in cache module
1.- sram address was wrong (leftover from previous version)
2.- writes to unmapped areas were blocking the cache
3.- Sequence SW,LW produced a RAW data hazard in some cases		 ja_rd 4780d 19h /ion/trunk
150 Bug fix: added missing nop in vacant branch delay slot ja_rd 4781d 17h /ion/trunk
149 changed size of simulated flash in opcodes sample code ja_rd 4781d 17h /ion/trunk
148 Added optional cache support to 'opcodes' test.
Updated simulation length accordingly.		 ja_rd 4783d 08h /ion/trunk
147 SW simulator updated to latest HW revision
(plus a few mistakes corrected: wrongly commented out lines, mostly)		 ja_rd 4783d 08h /ion/trunk
146 Added D-Cache setup code to 'adventure' bootstrap code
(redundant since common C startup code already does it but...)		 ja_rd 4783d 09h /ion/trunk
145 MAJOR UPDATE: first version of D-Cache ja_rd 4783d 09h /ion/trunk
144 Added cache setup code to common startup code
Important: the new cache won't work without this		 ja_rd 4783d 09h /ion/trunk
143 'adventure' sample by default will log from 0xb0000000
and simulation length is now longer		 ja_rd 4784d 23h /ion/trunk
142 'Adventure' bootstrap code now enables the cache
(and runs noticeably faster on DE-1 board)		 ja_rd 4784d 23h /ion/trunk

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