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[/] [ion/] [trunk/] - Rev 42

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Rev Log message Author Age Path
42 Added cache stub module, plus related test bench ja_rd 4898d 10h /ion/trunk
41 Updated main project doc ja_rd 4898d 10h /ion/trunk
40 pre-generated 'hello' demo updated ja_rd 4898d 10h /ion/trunk
39 Updated main project doc ja_rd 4898d 10h /ion/trunk
38 Minor changes in header comments ja_rd 4898d 11h /ion/trunk
37 functions added to package for standard address decoding ja_rd 4898d 11h /ion/trunk
36 pre-generated simulation test bench TB1 updated
for compatibility to other changes		 ja_rd 4898d 11h /ion/trunk
35 CPU mem_wait logic updated to work with cache ja_rd 4898d 11h /ion/trunk
34 default data address moved to 0x80000000
makefiles and readme files updated accordingly		 ja_rd 4898d 11h /ion/trunk
33 bin2hdl now can initialize 16-bit wide memories ja_rd 4898d 11h /ion/trunk
32 slite: catch 1-instruction endless loops
now can run unattended; will stop at the end of main()		 ja_rd 4898d 12h /ion/trunk
31 Major refactor in slite:
supports memory map with more than 1 block
indentation made homogeneous
unused code removed		 ja_rd 4898d 12h /ion/trunk
30 Completed decoding of instructions
(to prevent side effects of invalid opcodes)		 ja_rd 4900d 08h /ion/trunk
29 opcode test updated:
supports CP0 cause register and traps in delay slots
tests that traps abort next instruction in all cases		 ja_rd 4900d 09h /ion/trunk
28 Core updated:
supports CP0 cause register and traps in delay slots
traps abort next instruction in all cases (incl. jumps/L*/S*)		 ja_rd 4900d 09h /ion/trunk
27 SW simulator updated: now supports CP0 cause register and traps in delay slots ja_rd 4900d 10h /ion/trunk
26 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window		 ja_rd 4900d 14h /ion/trunk
25 opcode test:
HO and LO registers tested along with mul/div and not separately		 ja_rd 4900d 14h /ion/trunk
24 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window		 ja_rd 4900d 14h /ion/trunk
23 Unimplemented instruction are now trapped (barely tested) ja_rd 4900d 14h /ion/trunk

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