Rev |
Log message |
Author |
Age |
Path |
113 |
minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error
spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated
prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files |
rfajardo |
4607d 17h |
/minsoc/branches/verilator/utils |
112 |
Updating installation & configuration scripts. |
rfajardo |
4608d 08h |
/minsoc/branches/verilator/utils |
111 |
minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh |
rfajardo |
4608d 09h |
/minsoc/branches/verilator/utils |
110 |
Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure
-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0
-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.
-prj/src: or1200_top.prj downdated to definition of or1200_v1 |
rfajardo |
4608d 09h |
/minsoc/branches/verilator/utils |
109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4608d 11h |
/minsoc/branches/verilator/utils |
106 |
Installation script was checking the ENV variable before setting it. |
rfajardo |
4608d 20h |
/minsoc/branches/verilator/utils |
103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4618d 12h |
/minsoc/branches/verilator/utils |
102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4618d 12h |
/minsoc/branches/verilator/utils |
83 |
minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. |
rfajardo |
4670d 22h |
/minsoc/branches/verilator/utils |
82 |
minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. |
rfajardo |
4673d 21h |
/minsoc/branches/verilator/utils |
81 |
Installation script complete, nice text feedback, output logs and better execution order. |
rfajardo |
4674d 08h |
/minsoc/branches/verilator/utils |
79 |
minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated |
rfajardo |
4677d 13h |
/minsoc/branches/verilator/utils |
78 |
minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). |
rfajardo |
4677d 13h |
/minsoc/branches/verilator/utils |
77 |
New tool requirements for installing Icarus Verilog. |
rfajardo |
4677d 13h |
/minsoc/branches/verilator/utils |
76 |
Including a script allowing the installation of MinSoC and all its required tools.
It should be working for all Linuxes and Cygwin. |
rfajardo |
4677d 14h |
/minsoc/branches/verilator/utils |
64 |
firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.
Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
Backend:
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure
backend/spartan3a_dsp_kit:
-working on FPGA
backend/spartan3e_starter_kit:
-has to be tested
backend/ml509:
-missing files have to be copied and adapted, configure script has to be copied and adapted
backend/std:
-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable |
rfajardo |
4784d 20h |
/minsoc/branches/verilator/utils |
47 |
Firmware updated to work with gcc-4.5. It is actually working just fine and gcc-4.5 assembly code seems a lot cleaner.
I noticed that by increasing the free stack space for the interrupt handler by 130 made the resulting firmware not work. I assume it is because 130 is not aligned 130%4 = 2 and the stack simply does not work then. Instead I'm freeing the previous 116 plus 128 (for 32 registers as mentioned by Jeremy) and it works. |
rfajardo |
4827d 16h |
/minsoc/branches/verilator/utils |
46 |
Including an explanation of what has to be updated on gpio to port it smoothly to minsoc. |
rfajardo |
4827d 21h |
/minsoc/branches/verilator/utils |
45 |
A more stable version |
ConX. |
4828d 12h |
/minsoc/branches/verilator/utils |
44 |
Fixing some bugs. But it still works only in Debian/Ubuntu |
ConX. |
4828d 13h |
/minsoc/branches/verilator/utils |