Rev |
Log message |
Author |
Age |
Path |
100 |
added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated |
JonasDC |
4070d 12h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4343d 08h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
23 |
added descriptive comments |
JonasDC |
4343d 09h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4346d 03h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
21 |
changed x_i signal to xi |
JonasDC |
4347d 10h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4347d 11h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4352d 06h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4353d 05h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4353d 10h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
16 |
package with modified generic parameter for register_n |
JonasDC |
4353d 23h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
15 |
changed generic for register width from n to width for consistency |
JonasDC |
4353d 23h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
14 |
changed comments, file is now according to OC design rules |
JonasDC |
4354d 00h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4354d 00h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
12 |
updated comments, file is now completely according to design rules |
JonasDC |
4354d 00h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
10 |
changed signal input port names to correct name |
JonasDC |
4354d 05h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
9 |
added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names |
JonasDC |
4354d 05h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
8 |
added descriptive comments |
JonasDC |
4354d 07h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
7 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4354d 07h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
6 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4354d 08h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |
4 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4354d 10h |
/mod_sim_exp/tags/Release_1.0/rtl/vhdl |