URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] - Rev 67

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4172d 20h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4172d 21h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4180d 12h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4180d 18h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
62	not used anymore	JonasDC	4180d 21h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
61	updated comments, added optional altera constraint	JonasDC	4180d 21h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4183d 11h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4183d 11h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
55	updated resource usage in comments	JonasDC	4187d 11h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4187d 11h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
53	correctly inferred ram for altera dual port ram	JonasDC	4187d 18h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
52	correct inferring of blockram, no additional resources.	JonasDC	4187d 18h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
51	true dual port ram for xilinx	JonasDC	4187d 19h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4187d 19h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4267d 19h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4271d 12h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
43	made the core parameters generics	JonasDC	4271d 12h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4277d 20h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
41	removed deprecated files from version control	JonasDC	4277d 20h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl
40	adjusted core instantiation to new core module name	JonasDC	4286d 00h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] - Rev 67

Filtering Options