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220 More revision sections added jshamlet 1537d 07h /open8_urisc
219 Added revision block and corrected creation date. jshamlet 1537d 07h /open8_urisc
218 Revision sections added,
vdsm8.vhd added.		 jshamlet 1537d 07h /open8_urisc
217 Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup.		 jshamlet 1537d 08h /open8_urisc
216 Fixed missing parenthesis jshamlet 1537d 10h /open8_urisc
215 More code cleanup jshamlet 1537d 10h /open8_urisc
214 Initial add of some older code jshamlet 1541d 08h /open8_urisc
213 Code and comment cleanup jshamlet 1541d 09h /open8_urisc
212 Fixed issue with rewritten epoch timer not clearing alarm on set point write. jshamlet 1541d 15h /open8_urisc
211 Ok, this time with feeling. Timer should now properly reset on interval update. jshamlet 1542d 12h /open8_urisc
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.		 jshamlet 1542d 15h /open8_urisc
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1543d 03h /open8_urisc
208 Removed unnecessary package references jshamlet 1543d 13h /open8_urisc
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1544d 06h /open8_urisc
206 Merged interrupt logic with other clocked process. jshamlet 1548d 01h /open8_urisc
205 More code and comment cleanup for the new SDLC engine jshamlet 1548d 01h /open8_urisc
204 Fixed more incorrect comments jshamlet 1548d 01h /open8_urisc
203 Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. jshamlet 1548d 07h /open8_urisc
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.		 jshamlet 1548d 08h /open8_urisc
201 Fixed comments regarding RX Checksum location jshamlet 1550d 05h /open8_urisc

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