| Rev |
Log message |
Author |
Age |
Path |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4499d 08h |
/openmsp430/trunk/core/rtl/verilog |
| 132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4512d 07h |
/openmsp430/trunk/core/rtl/verilog |
| 130 |
Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) |
olivier.girard |
4520d 06h |
/openmsp430/trunk/core/rtl/verilog |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4596d 07h |
/openmsp430/trunk/core/rtl/verilog |
| 117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4772d 09h |
/openmsp430/trunk/core/rtl/verilog |
| 112 |
Modified comment. |
olivier.girard |
4805d 08h |
/openmsp430/trunk/core/rtl/verilog |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4806d 08h |
/openmsp430/trunk/core/rtl/verilog |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4862d 06h |
/openmsp430/trunk/core/rtl/verilog |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4877d 07h |
/openmsp430/trunk/core/rtl/verilog |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4882d 13h |
/openmsp430/trunk/core/rtl/verilog |
| 102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4883d 06h |
/openmsp430/trunk/core/rtl/verilog |
| 101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4883d 08h |
/openmsp430/trunk/core/rtl/verilog |
| 91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4895d 08h |
/openmsp430/trunk/core/rtl/verilog |
| 86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4918d 05h |
/openmsp430/trunk/core/rtl/verilog |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4918d 07h |
/openmsp430/trunk/core/rtl/verilog |
| 84 |
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface. |
olivier.girard |
4923d 08h |
/openmsp430/trunk/core/rtl/verilog |
| 79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
4984d 09h |
/openmsp430/trunk/core/rtl/verilog |
| 74 |
Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly. |
olivier.girard |
5071d 08h |
/openmsp430/trunk/core/rtl/verilog |
| 72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5098d 09h |
/openmsp430/trunk/core/rtl/verilog |
| 67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5245d 16h |
/openmsp430/trunk/core/rtl/verilog |
