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[/] [openmsp430/] [trunk/] [fpga/] - Rev 148

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143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4427d 14h /openmsp430/trunk/fpga
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4443d 23h /openmsp430/trunk/fpga
136 Update all FPGA projects with the latest core version. olivier.girard 4475d 13h /openmsp430/trunk/fpga
132 Update FPGA examples with the POP.B bug fix olivier.girard 4488d 14h /openmsp430/trunk/fpga
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4572d 13h /openmsp430/trunk/fpga
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4716d 14h /openmsp430/trunk/fpga
112 Modified comment. olivier.girard 4781d 14h /openmsp430/trunk/fpga
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4782d 14h /openmsp430/trunk/fpga
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4836d 23h /openmsp430/trunk/fpga
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4838d 12h /openmsp430/trunk/fpga
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4838d 12h /openmsp430/trunk/fpga
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4838d 13h /openmsp430/trunk/fpga
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4853d 13h /openmsp430/trunk/fpga
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4857d 15h /openmsp430/trunk/fpga
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4862d 13h /openmsp430/trunk/fpga
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4863d 14h /openmsp430/trunk/fpga
96 Fixed EraseROM command in the TCL library of the Software development tools. olivier.girard 4864d 14h /openmsp430/trunk/fpga
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4867d 14h /openmsp430/trunk/fpga
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4871d 15h /openmsp430/trunk/fpga
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4894d 12h /openmsp430/trunk/fpga

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