OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 197

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
197 Fixed bug in memory allocator. jeremybennett 5137d 12h /openrisc
196 Fixed name for newlib install option. jeremybennett 5137d 12h /openrisc
195 Adding linux and uClibc paths back for patches, updated gnu-src build script making newlib an option (off by deafult) julius 5137d 13h /openrisc
194 Tidied up code setjmp and longjmp into their own files, and adjusted Makefile accordingly. Simplified cache setup in startup code. Replaced calls via register with calls using immediate address. jeremybennett 5138d 06h /openrisc
193 Record changes to initfini.c jeremybennett 5138d 06h /openrisc
192 Updated to fix problems with initfini assembler fragments. jeremybennett 5138d 06h /openrisc
191 Updated to clarify use of r9 in the l.jalr delay slot. jeremybennett 5138d 07h /openrisc
190 Allow the Or1ksim installation directory to be set by option. jeremybennett 5138d 12h /openrisc
189 Fuller explanation of the build script given. jeremybennett 5138d 12h /openrisc
188 More rigorous testing of options. jeremybennett 5138d 13h /openrisc
187 Or1200 sprs FPU update julius 5140d 06h /openrisc
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5140d 09h /openrisc
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5140d 10h /openrisc
184 Fix the UART version of newlib. jeremybennett 5141d 14h /openrisc
183 Fix to setjmp, so it works. Some commenting tidy ups elsewhere. jeremybennett 5142d 06h /openrisc
182 Removed redundant code. jeremybennett 5142d 06h /openrisc
181 Updated, so only GCC tries to use parallel build. Redundant target for libgcc removed. jeremybennett 5142d 09h /openrisc
180 Rewritten to use namespace clean BSP in libgloss. Two versions of the library, one with, one without using the UART. jeremybennett 5142d 09h /openrisc
179 Code is now loaded from address 0, with section .vectors loaded before any other section. This provides a convenient mechanism for setting up the OR1K exception vectors. jeremybennett 5142d 09h /openrisc
178 Fixes a bug in prologue recognition without frame pointer. jeremybennett 5142d 09h /openrisc

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.