OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] - Rev 123

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5174d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
122 Added l.ror and l.rori with associated tests. jeremybennett 5175d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5175d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5175d 22h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5178d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5179d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5179d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5180d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
110 or1ksim make check should work without a libc in the or32-elf tools julius 5181d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5183d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
106 Removing old tests, pending addition of new ones. jeremybennett 5183d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
104 Candidate release 0.4.0rc4 jeremybennett 5186d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5195d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
100 Single precision FPU stuff for or1ksim julius 5195d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
99 Bug in test evaluation for library fixed. jeremybennett 5200d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5201d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5215d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
96 Various changes which had not been picked up in earlier commits. jeremybennett 5216d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
95 Some tidy ups to the DejaGNU testing.

All Mark Jarvin's fixes for Mac OS X.		 jeremybennett 5218d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5222d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.