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[/] [openrisc/] [trunk/] - Rev 496

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Rev Log message Author Age Path
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4859d 21h /openrisc/trunk
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 4859d 21h /openrisc/trunk
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4870d 15h /openrisc/trunk
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 4872d 23h /openrisc/trunk
492 ORPSoC VPI interface for modelsim and documentation update julius 4873d 21h /openrisc/trunk
491 ORPSoC or1200_monitor update. julius 4874d 08h /openrisc/trunk
490 Updates to fix spurious test failures and register scheduling. jeremybennett 4878d 13h /openrisc/trunk
489 ORPSoC sw cleanup. Remove warnings. julius 4883d 20h /openrisc/trunk
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4883d 21h /openrisc/trunk
487 ORPSoC main software makefile update julius 4886d 18h /openrisc/trunk
486 ORPSoC updates, mainly software, i2c driver julius 4886d 19h /openrisc/trunk
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4890d 23h /openrisc/trunk
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 4891d 21h /openrisc/trunk
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4893d 23h /openrisc/trunk
482 Don't hardcode tool versions in help text olof 4895d 11h /openrisc/trunk
481 OR1200 Update. RTL and spec. julius 4907d 06h /openrisc/trunk
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4908d 03h /openrisc/trunk
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4909d 03h /openrisc/trunk
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4910d 19h /openrisc/trunk
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4911d 03h /openrisc/trunk

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