OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 64

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5284d 17h /openrisc/trunk
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5294d 14h /openrisc/trunk
62 This material is part of the separate website downloads directory. jeremybennett 5305d 17h /openrisc/trunk
61 The build directory should not be part of the SVN configuration. jeremybennett 5305d 17h /openrisc/trunk
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5312d 10h /openrisc/trunk
59 Toolchain install script gcc patch change and gdb configure change julius 5333d 11h /openrisc/trunk
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5336d 09h /openrisc/trunk
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5341d 13h /openrisc/trunk
56 adding generic pll model to orpsoc julius 5349d 16h /openrisc/trunk
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5352d 06h /openrisc/trunk
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5362d 13h /openrisc/trunk
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5380d 14h /openrisc/trunk
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5381d 10h /openrisc/trunk
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5395d 12h /openrisc/trunk
50 Adding or32_funcs.S julius 5395d 16h /openrisc/trunk
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5414d 06h /openrisc/trunk
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5414d 09h /openrisc/trunk
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5423d 17h /openrisc/trunk
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5429d 17h /openrisc/trunk
45 Orpsoc eth test fix and script error message update julius 5436d 17h /openrisc/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.