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858 orpsoc/tests: Fix or1200-dsxinsn when caches are not present

This test would go into an endless loop when caches are not present.		 stekern 4107d 23h /openrisc/trunk
857 orpsocv2: remove reference to r32 in context save/restore julius 4117d 13h /openrisc/trunk
856 Fixed rounding of UART divisor skrzyp 4161d 16h /openrisc/trunk
855 Publish OR1K 1.0 architecture spec julius 4204d 15h /openrisc/trunk
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4214d 09h /openrisc/trunk
853 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4239d 18h /openrisc/trunk
852 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4239d 18h /openrisc/trunk
851 changed branch delay flags skrzyp 4242d 17h /openrisc/trunk
850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4254d 10h /openrisc/trunk
849 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4254d 10h /openrisc/trunk
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4254d 10h /openrisc/trunk
847 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4254d 10h /openrisc/trunk
846 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4254d 10h /openrisc/trunk
845 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4254d 10h /openrisc/trunk
844 skrzyp 4255d 03h /openrisc/trunk
843 Applied RDiez suggestions skrzyp 4255d 03h /openrisc/trunk
842 Moving GDB 7.1 into the old collection. jeremybennett 4257d 01h /openrisc/trunk
841 GDB 7.2 is now considered the stable version. jeremybennett 4257d 01h /openrisc/trunk
840 Relocate GDB 6.8 to the old directory. jeremybennett 4257d 01h /openrisc/trunk
839 Forgot about updating linker flags, thanks RDiez! skrzyp 4258d 04h /openrisc/trunk

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