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Rev Log message Author Age Path
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4974d 01h /openrisc/trunk
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.		 julius 4974d 05h /openrisc/trunk
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4977d 00h /openrisc/trunk
427 Fixes for C++ to correspond to fixes in uClibc. jeremybennett 4978d 09h /openrisc/trunk
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4979d 19h /openrisc/trunk
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4979d 20h /openrisc/trunk
424 C++ library, needed for C++ compiler. jeremybennett 4980d 06h /openrisc/trunk
423 Minor typo fixed. jeremybennett 4980d 09h /openrisc/trunk
422 Separates out --force actions, so only build dirs corresponding to targets being built are blown away. jeremybennett 4980d 09h /openrisc/trunk
421 Fixing some typos in bld-all.sh's --help printout and changed all
"cd .." lines to "cd -".		 julius 4983d 07h /openrisc/trunk
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4985d 05h /openrisc/trunk
419 ORPmon: Fixed interrupt routines in reset.S so they are compatible with new
GCC port (skip over redzone).
Added some defines to easily switch what is done when an error vector
is executed.
Added ability to print out EPCR when crashing.
Changed linker script back to one which doesn't skip over holes in SPI
flash memories.		 julius 4985d 08h /openrisc/trunk
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4985d 08h /openrisc/trunk
417 ORPSoC re-adding doc automake files, this time not symlinks julius 4988d 05h /openrisc/trunk
416 ORPSoC doc cleanup - removing symlinks from automake'd docs build path julius 4988d 05h /openrisc/trunk
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4988d 05h /openrisc/trunk
414 Updates to add -mredzone and improved GCC optimizations. jeremybennett 4989d 00h /openrisc/trunk
413 Fixed to combined bug in the assembler and linker. jeremybennett 4990d 03h /openrisc/trunk
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4991d 19h /openrisc/trunk
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4992d 07h /openrisc/trunk

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