OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] - Rev 459

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4949d 17h /openrisc/trunk
458 or1ksim testsuite updates julius 4950d 15h /openrisc/trunk
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4959d 06h /openrisc/trunk
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4959d 07h /openrisc/trunk
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4963d 09h /openrisc/trunk
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4965d 11h /openrisc/trunk
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4965d 22h /openrisc/trunk
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4966d 06h /openrisc/trunk
451 More tidying up. jeremybennett 4970d 02h /openrisc/trunk
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4970d 05h /openrisc/trunk
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4972d 02h /openrisc/trunk
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4972d 12h /openrisc/trunk
447 Updates to register order. jeremybennett 4973d 06h /openrisc/trunk
446 gdb-7.2 gdbserver updates. julius 4974d 01h /openrisc/trunk
445 gdbserver update to use kernel port ptrace register definitions. julius 4974d 21h /openrisc/trunk
444 Changes to ABI handling of varargs. jeremybennett 4975d 06h /openrisc/trunk
443 Work in progress on more efficient Ethernet. jeremybennett 4975d 10h /openrisc/trunk
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4976d 00h /openrisc/trunk
441 Changes for gdbserver. jeremybennett 4976d 07h /openrisc/trunk
440 Updated documentation to describe new Ethernet usage. jeremybennett 4977d 02h /openrisc/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.