| Rev |
Log message |
Author |
Age |
Path |
| 815 |
OR1200 debug unit: prevent deadlock when trap instruction stalls
As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.
The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result. |
yannv |
4297d 17h |
/openrisc/trunk/or1200/rtl/verilog |
| 813 |
or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4312d 09h |
/openrisc/trunk/or1200/rtl/verilog |
| 808 |
OR1200: Add DSX bit support to SR.
Updated documentation, revision is now 13.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85 |
julius |
4428d 03h |
/openrisc/trunk/or1200/rtl/verilog |
| 806 |
OR1200: Fix for bug 90
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4428d 03h |
/openrisc/trunk/or1200/rtl/verilog |
| 804 |
OR1200: Fix for bug 91
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4428d 03h |
/openrisc/trunk/or1200/rtl/verilog |
| 802 |
OR1200: Fix for bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4433d 09h |
/openrisc/trunk/or1200/rtl/verilog |
| 794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4466d 18h |
/openrisc/trunk/or1200/rtl/verilog |
| 788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4491d 08h |
/openrisc/trunk/or1200/rtl/verilog |
| 679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4515d 08h |
/openrisc/trunk/or1200/rtl/verilog |
| 674 |
or1200: Fix for Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled |
julius |
4557d 17h |
/openrisc/trunk/or1200/rtl/verilog |
| 644 |
or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled |
julius |
4696d 08h |
/openrisc/trunk/or1200/rtl/verilog |
| 643 |
or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix |
julius |
4696d 08h |
/openrisc/trunk/or1200/rtl/verilog |
| 642 |
or1200: add carry, overflow bits, and range exception |
julius |
4696d 08h |
/openrisc/trunk/or1200/rtl/verilog |
| 641 |
or1200: fix serial multiply/divide bug |
julius |
4696d 08h |
/openrisc/trunk/or1200/rtl/verilog |
| 640 |
or1200: add l.ext instructions, fix a MAC bug |
julius |
4696d 08h |
/openrisc/trunk/or1200/rtl/verilog |
| 639 |
or1200: or1200_dpram.v change task set_gpr to function |
julius |
4696d 08h |
/openrisc/trunk/or1200/rtl/verilog |
| 481 |
OR1200 Update. RTL and spec. |
julius |
4922d 00h |
/openrisc/trunk/or1200/rtl/verilog |
| 401 |
Fixing find first one (ff1) and find last one (fl1) support in OR1200.
Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table. |
julius |
5000d 12h |
/openrisc/trunk/or1200/rtl/verilog |
| 364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5050d 09h |
/openrisc/trunk/or1200/rtl/verilog |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5052d 17h |
/openrisc/trunk/or1200/rtl/verilog |
