OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] - Rev 569

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
556 or1ksim - added performance counters unit and test for it. julius 4770d 23h /openrisc/trunk/or1ksim/testsuite
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4799d 04h /openrisc/trunk/or1ksim/testsuite
532 Ensure the halted flag is cleared when the processor is unstalled. jeremybennett 4810d 00h /openrisc/trunk/or1ksim/testsuite
510 Updates for release 0.5.1rc1. jeremybennett 4830d 07h /openrisc/trunk/or1ksim/testsuite
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4831d 07h /openrisc/trunk/or1ksim/testsuite
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4873d 00h /openrisc/trunk/or1ksim/testsuite
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4896d 09h /openrisc/trunk/or1ksim/testsuite
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4923d 08h /openrisc/trunk/or1ksim/testsuite
458 or1ksim testsuite updates julius 4924d 13h /openrisc/trunk/or1ksim/testsuite
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4933d 03h /openrisc/trunk/or1ksim/testsuite
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4944d 03h /openrisc/trunk/or1ksim/testsuite
440 Updated documentation to describe new Ethernet usage. jeremybennett 4950d 23h /openrisc/trunk/or1ksim/testsuite
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4959d 18h /openrisc/trunk/or1ksim/testsuite
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4963d 00h /openrisc/trunk/or1ksim/testsuite
433 New single program interrupt test programs. jeremybennett 4964d 02h /openrisc/trunk/or1ksim/testsuite
432 Updates to handle interrupts correctly. jeremybennett 4964d 03h /openrisc/trunk/or1ksim/testsuite
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4969d 23h /openrisc/trunk/or1ksim/testsuite
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4978d 04h /openrisc/trunk/or1ksim/testsuite
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4978d 07h /openrisc/trunk/or1ksim/testsuite
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 5018d 04h /openrisc/trunk/or1ksim/testsuite

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.