OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 119

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
111 Changed conditionals for Verilator to "verilator" instead of "VERILATOR". jeremybennett 5131d 23h /openrisc/trunk/orpsocv2
78 Fixed typo in Silos workaround script rherveille 5194d 18h /openrisc/trunk/orpsocv2
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5194d 19h /openrisc/trunk/orpsocv2
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5195d 18h /openrisc/trunk/orpsocv2
71 ORPSoC board builds, adding readmes julius 5238d 04h /openrisc/trunk/orpsocv2
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5242d 09h /openrisc/trunk/orpsocv2
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5242d 10h /openrisc/trunk/orpsocv2
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5245d 01h /openrisc/trunk/orpsocv2
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5245d 04h /openrisc/trunk/orpsocv2
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5265d 02h /openrisc/trunk/orpsocv2
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5269d 08h /openrisc/trunk/orpsocv2
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5272d 03h /openrisc/trunk/orpsocv2
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5282d 00h /openrisc/trunk/orpsocv2
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5323d 20h /openrisc/trunk/orpsocv2
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5329d 00h /openrisc/trunk/orpsocv2
56 adding generic pll model to orpsoc julius 5337d 02h /openrisc/trunk/orpsocv2
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5339d 17h /openrisc/trunk/orpsocv2
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5350d 00h /openrisc/trunk/orpsocv2
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5368d 00h /openrisc/trunk/orpsocv2
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5368d 20h /openrisc/trunk/orpsocv2

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.