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[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 381

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Rev	Log message	Author	Age	Path
374	ORPSoCv2 adding some files forgotten from last checkin	julius	5013d 17h	/openrisc/trunk/orpsocv2
373	ORPSoCv2 software update for compatibility with OR toolchain 1.0	julius	5013d 17h	/openrisc/trunk/orpsocv2
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5025d 15h	/openrisc/trunk/orpsocv2
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5026d 01h	/openrisc/trunk/orpsocv2
362	ORPSoCv2 verilator building working again. Board build fixes to follow	julius	5027d 10h	/openrisc/trunk/orpsocv2
361	OPRSoCv2 - adding things left out in last check-in	julius	5027d 14h	/openrisc/trunk/orpsocv2
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5027d 15h	/openrisc/trunk/orpsocv2
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5027d 23h	/openrisc/trunk/orpsocv2
356	Added new simple MAC test to ORPSoC test suite: * orpsocv2/sw/or1200asm/or1200asm-mac.S: Added Fixed MAC pipeline issue in OR1200 * or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn. * orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: "" * orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version * orpsocv2/sim/bin/Makefile: Added new MAC test to default tests	julius	5028d 09h	/openrisc/trunk/orpsocv2
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5029d 14h	/openrisc/trunk/orpsocv2
353	OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: "" * or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: "" * or1200/rtl/verilog/or1200_except.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_except.v: "" * orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some Verilator related Lint issues fixed. ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and updated RAM model hooks for new RAM. * orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping * orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: "" * orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping, change include and classes for new RAM model. * orpsocv2/bench/sysc/src/OrpsocAccess.cpp: "" or_debug_proxy - fixing sleep and Windows make issues: * or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly * or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated) ORPmon play around, various changes to low level files.	julius	5029d 17h	/openrisc/trunk/orpsocv2
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5030d 15h	/openrisc/trunk/orpsocv2
350	Adding new OR1200 processor to ORPSoCv2	julius	5030d 19h	/openrisc/trunk/orpsocv2
349	ORPSoCv2 update with new software and makefile update	julius	5030d 19h	/openrisc/trunk/orpsocv2
348	First stage of ORPSoCv2 update - more to come	julius	5030d 19h	/openrisc/trunk/orpsocv2
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5088d 17h	/openrisc/trunk/orpsocv2
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5120d 19h	/openrisc/trunk/orpsocv2
78	Fixed typo in Silos workaround script	rherveille	5183d 14h	/openrisc/trunk/orpsocv2
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5183d 14h	/openrisc/trunk/orpsocv2
76	Added: +libext+.v Added: +incdir+.	rherveille	5184d 14h	/openrisc/trunk/orpsocv2

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[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 381

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