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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] - Rev 125

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Rev Log message Author Age Path
78 Fixed typo in Silos workaround script rherveille 5205d 04h /openrisc/trunk/orpsocv2/sim/bin
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour
rherveille 5205d 04h /openrisc/trunk/orpsocv2/sim/bin
76 Added: +libext+.v
Added: +incdir+.
rherveille 5206d 03h /openrisc/trunk/orpsocv2/sim/bin
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5252d 18h /openrisc/trunk/orpsocv2/sim/bin
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5252d 19h /openrisc/trunk/orpsocv2/sim/bin
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5255d 10h /openrisc/trunk/orpsocv2/sim/bin
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5255d 13h /openrisc/trunk/orpsocv2/sim/bin
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5275d 11h /openrisc/trunk/orpsocv2/sim/bin
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5282d 13h /openrisc/trunk/orpsocv2/sim/bin
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5292d 10h /openrisc/trunk/orpsocv2/sim/bin
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5334d 05h /openrisc/trunk/orpsocv2/sim/bin
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5339d 09h /openrisc/trunk/orpsocv2/sim/bin
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5350d 02h /openrisc/trunk/orpsocv2/sim/bin
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5360d 09h /openrisc/trunk/orpsocv2/sim/bin
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5378d 10h /openrisc/trunk/orpsocv2/sim/bin
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5393d 08h /openrisc/trunk/orpsocv2/sim/bin
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5412d 02h /openrisc/trunk/orpsocv2/sim/bin
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5463d 12h /openrisc/trunk/orpsocv2/sim/bin
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5487d 09h /openrisc/trunk/orpsocv2/sim/bin
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5503d 06h /openrisc/trunk/orpsocv2/sim/bin

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