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[/] [or1k/] [tags/] [nog_patch_35] - Rev 996

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Rev	Log message	Author	Age	Path
996	some minor bugs fixed	markom	7998d 02h	/or1k/tags/nog_patch_35
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7998d 09h	/or1k/tags/nog_patch_35
993	Fixed IMMU bug.	lampret	7998d 09h	/or1k/tags/nog_patch_35
992	A bug when cache enabled and bus error comes fixed.	simons	7998d 19h	/or1k/tags/nog_patch_35
991	Different memory controller.	simons	7998d 19h	/or1k/tags/nog_patch_35
990	Test is now complete.	simons	7998d 19h	/or1k/tags/nog_patch_35
989	c++ is making problems so, for now, it is excluded.	simons	8000d 03h	/or1k/tags/nog_patch_35
988	ORP architecture supported.	simons	8000d 18h	/or1k/tags/nog_patch_35
987	ORP architecture supported.	simons	8001d 01h	/or1k/tags/nog_patch_35
986	outputs out of function are not registered anymore	markom	8001d 02h	/or1k/tags/nog_patch_35
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8001d 14h	/or1k/tags/nog_patch_35
984	Disable SB until it is tested	lampret	8001d 14h	/or1k/tags/nog_patch_35
983	First checkin	lampret	8001d 16h	/or1k/tags/nog_patch_35
982	Moved to sim/bin	lampret	8001d 16h	/or1k/tags/nog_patch_35
981	First checkin.	lampret	8001d 16h	/or1k/tags/nog_patch_35
980	Removed sim.tcl that shouldn't be here.	lampret	8001d 16h	/or1k/tags/nog_patch_35
979	Removed old test case binaries.	lampret	8001d 16h	/or1k/tags/nog_patch_35
978	Added variable delay for SRAM.	lampret	8001d 16h	/or1k/tags/nog_patch_35
977	Added store buffer.	lampret	8001d 16h	/or1k/tags/nog_patch_35
976	Added store buffer	lampret	8001d 16h	/or1k/tags/nog_patch_35

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[/] [or1k/] [tags/] [nog_patch_35] - Rev 996

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