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[/] [or1k/] [tags/] [nog_patch_61] - Rev 994

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Rev	Log message	Author	Age	Path
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7998d 05h	/or1k/tags/nog_patch_61
993	Fixed IMMU bug.	lampret	7998d 05h	/or1k/tags/nog_patch_61
992	A bug when cache enabled and bus error comes fixed.	simons	7998d 14h	/or1k/tags/nog_patch_61
991	Different memory controller.	simons	7998d 14h	/or1k/tags/nog_patch_61
990	Test is now complete.	simons	7998d 14h	/or1k/tags/nog_patch_61
989	c++ is making problems so, for now, it is excluded.	simons	7999d 22h	/or1k/tags/nog_patch_61
988	ORP architecture supported.	simons	8000d 14h	/or1k/tags/nog_patch_61
987	ORP architecture supported.	simons	8000d 21h	/or1k/tags/nog_patch_61
986	outputs out of function are not registered anymore	markom	8000d 22h	/or1k/tags/nog_patch_61
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8001d 09h	/or1k/tags/nog_patch_61
984	Disable SB until it is tested	lampret	8001d 09h	/or1k/tags/nog_patch_61
983	First checkin	lampret	8001d 11h	/or1k/tags/nog_patch_61
982	Moved to sim/bin	lampret	8001d 11h	/or1k/tags/nog_patch_61
981	First checkin.	lampret	8001d 11h	/or1k/tags/nog_patch_61
980	Removed sim.tcl that shouldn't be here.	lampret	8001d 11h	/or1k/tags/nog_patch_61
979	Removed old test case binaries.	lampret	8001d 11h	/or1k/tags/nog_patch_61
978	Added variable delay for SRAM.	lampret	8001d 12h	/or1k/tags/nog_patch_61
977	Added store buffer.	lampret	8001d 12h	/or1k/tags/nog_patch_61
976	Added store buffer	lampret	8001d 12h	/or1k/tags/nog_patch_61
975	First checkin	lampret	8001d 12h	/or1k/tags/nog_patch_61

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[/] [or1k/] [tags/] [nog_patch_61] - Rev 994

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