URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1] - Rev 197

Rev	Log message	Author	Age	Path
197	This is not used any more.	simons	8347d 11h	/or1k/tags/rel_1
196	Configuration SPRs added.	simons	8347d 11h	/or1k/tags/rel_1
195	New test added.	simons	8347d 11h	/or1k/tags/rel_1
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8347d 19h	/or1k/tags/rel_1
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8347d 19h	/or1k/tags/rel_1
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8348d 04h	/or1k/tags/rel_1
191	Added UART jitter var to sim config	chris	8349d 01h	/or1k/tags/rel_1
190	Added jitter initialization	chris	8349d 01h	/or1k/tags/rel_1
189	fixed mode handling for tick facility	chris	8349d 01h	/or1k/tags/rel_1
188	fixed PIC interrupt controller	chris	8349d 01h	/or1k/tags/rel_1
187	minor change to clear pending exception	chris	8349d 01h	/or1k/tags/rel_1
186	major change to UART structure	chris	8349d 01h	/or1k/tags/rel_1
185	major change to UART code	chris	8349d 01h	/or1k/tags/rel_1
184	modified decode for trace debugging	chris	8349d 01h	/or1k/tags/rel_1
183	changed special case for PICSR	chris	8349d 01h	/or1k/tags/rel_1
182	updated exception handling procedures	chris	8349d 01h	/or1k/tags/rel_1
181	Added trace/stall commands	chris	8349d 01h	/or1k/tags/rel_1
180	Updated debug.	lampret	8349d 07h	/or1k/tags/rel_1
179	Sim run script	lampret	8368d 23h	/or1k/tags/rel_1
178	Some test code	lampret	8368d 23h	/or1k/tags/rel_1