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[/] [or1k/] [tags/] [rel_5/] - Rev 895

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Rev Log message Author Age Path
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8101d 16h /or1k/tags/rel_5
894 Typing mistake fixed. simons 8103d 14h /or1k/tags/rel_5
893 Ethernet tested on xess board. simons 8103d 14h /or1k/tags/rel_5
891 eth_ledc not positioned correctly. Fixed. mohor 8103d 15h /or1k/tags/rel_5
890 Ethernet RXD pins were not positioned correctly. mohor 8103d 15h /or1k/tags/rel_5
889 Modified Ethernet model. ivang 8103d 20h /or1k/tags/rel_5
888 LCD 320x240 configuration added. simons 8104d 13h /or1k/tags/rel_5
887 Some additional instructions fixes. simons 8104d 23h /or1k/tags/rel_5
886 MMU registers reserved fields protected from writing. simons 8105d 22h /or1k/tags/rel_5
885 Some incorrect instructions fixed. simons 8106d 01h /or1k/tags/rel_5
884 code cleaning - a lot of global variables moved to runtime struct markom 8106d 04h /or1k/tags/rel_5
883 cuc updated, cuc prompt parsing; CSM analysis markom 8106d 23h /or1k/tags/rel_5
882 Routine for adjusting read and write delay for devices added. simons 8109d 02h /or1k/tags/rel_5
881 Normally uart rx and tx files should be in the current folder. mohor 8109d 19h /or1k/tags/rel_5
880 Library should not be erased during clean. mohor 8109d 20h /or1k/tags/rel_5
879 Initial version of OpenRISC Custom Unit Compiler added markom 8111d 22h /or1k/tags/rel_5
878 first release of atabug rherveille 8113d 15h /or1k/tags/rel_5
877 ata beta release rherveille 8113d 16h /or1k/tags/rel_5
876 Beta release of ATA simulation rherveille 8113d 16h /or1k/tags/rel_5
875 libgcc is moved here to avoid the mess with the folders. simons 8114d 04h /or1k/tags/rel_5

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