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[/] [or1k/] [tags/] [rel_5/] [or1200/] - Rev 736

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736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8159d 05h /or1k/tags/rel_5/or1200
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8159d 05h /or1k/tags/rel_5/or1200
668 Lapsus fixed. simons 8183d 15h /or1k/tags/rel_5/or1200
663 No longer using async rst as sync reset for the counter. lampret 8186d 05h /or1k/tags/rel_5/or1200
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8187d 02h /or1k/tags/rel_5/or1200
636 Fixed combinational loops. lampret 8196d 11h /or1k/tags/rel_5/or1200
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8201d 05h /or1k/tags/rel_5/or1200
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8205d 23h /or1k/tags/rel_5/or1200
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8209d 16h /or1k/tags/rel_5/or1200
596 SR[TEE] should be zero after reset. lampret 8209d 21h /or1k/tags/rel_5/or1200
595 Fixed 'the NPC single-step fix'. lampret 8210d 16h /or1k/tags/rel_5/or1200
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8210d 23h /or1k/tags/rel_5/or1200
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8214d 00h /or1k/tags/rel_5/or1200
571 Changed alignment exception EPCR. Not tested yet. lampret 8214d 09h /or1k/tags/rel_5/or1200
570 Fixed order of syscall and range exceptions. lampret 8214d 11h /or1k/tags/rel_5/or1200
569 Default ASIC configuration does not sample WB inputs. lampret 8214d 21h /or1k/tags/rel_5/or1200
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8215d 00h /or1k/tags/rel_5/or1200
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8221d 06h /or1k/tags/rel_5/or1200
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8225d 09h /or1k/tags/rel_5/or1200
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8225d 22h /or1k/tags/rel_5/or1200

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