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[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 641

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Rev Log message Author Age Path
641 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8224d 08h /or1k/tags/stable_0_2_0
640 Merge profiler and mprofiler with sim. ivang 8224d 09h /or1k/tags/stable_0_2_0
639 MMU cache inhibit bit test added. simons 8227d 00h /or1k/tags/stable_0_2_0
638 TLBTR CI bit is now working properly. simons 8227d 00h /or1k/tags/stable_0_2_0
637 Updated file names. lampret 8227d 01h /or1k/tags/stable_0_2_0
636 Fixed combinational loops. lampret 8227d 01h /or1k/tags/stable_0_2_0
635 Fixed Makefile bug. ivang 8227d 03h /or1k/tags/stable_0_2_0
634 configure.in : fixed to build start/Makefile
start.S : l.jalr r9 -> l.jr r9

Added missing files.		 ivang 8228d 04h /or1k/tags/stable_0_2_0
633 Bug fix in command line parser. ivang 8228d 05h /or1k/tags/stable_0_2_0
632 profiler and mprofiler merged into sim. ivang 8229d 00h /or1k/tags/stable_0_2_0
631 Real cache access is simulated now. simons 8229d 23h /or1k/tags/stable_0_2_0
630 some bug fixes in store buffer analysis markom 8230d 08h /or1k/tags/stable_0_2_0
629 typo fixed markom 8230d 11h /or1k/tags/stable_0_2_0
627 or32 restored markom 8230d 12h /or1k/tags/stable_0_2_0
626 store buffer added markom 8230d 12h /or1k/tags/stable_0_2_0
625 Bus error bug fixed. Cache routines added. simons 8231d 04h /or1k/tags/stable_0_2_0
624 Added logging of writes/read to/from SPR registers. ivang 8231d 05h /or1k/tags/stable_0_2_0
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8231d 07h /or1k/tags/stable_0_2_0
622 Cache test works on hardware. simons 8231d 10h /or1k/tags/stable_0_2_0
621 Cache test works on hardware. simons 8231d 11h /or1k/tags/stable_0_2_0

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