URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] - Rev 90

Rev	Log message	Author	Age	Path
90	Added tick timer.	lampret	8502d 15h	/or1k/tags/stable_0_2_0_rc1
89	Minor changes.	lampret	8503d 12h	/or1k/tags/stable_0_2_0_rc1
88	Update.	lampret	8503d 22h	/or1k/tags/stable_0_2_0_rc1
87	Files required for creation of html files.	lampret	8503d 23h	/or1k/tags/stable_0_2_0_rc1
86	Added dh command.	lampret	8503d 23h	/or1k/tags/stable_0_2_0_rc1
85	Added dumphex.	lampret	8503d 23h	/or1k/tags/stable_0_2_0_rc1
84	Update.	lampret	8503d 23h	/or1k/tags/stable_0_2_0_rc1
83	Updates.	lampret	8503d 23h	/or1k/tags/stable_0_2_0_rc1
82	Changed pctemp to pcnext.	lampret	8503d 23h	/or1k/tags/stable_0_2_0_rc1
80	First import.	lampret	8531d 18h	/or1k/tags/stable_0_2_0_rc1
79	Data and instruction cache simulation added.	lampret	8533d 15h	/or1k/tags/stable_0_2_0_rc1
78	(i/d)tlb_status	lampret	8657d 05h	/or1k/tags/stable_0_2_0_rc1
77	Regular update.	lampret	8657d 05h	/or1k/tags/stable_0_2_0_rc1
76	regular update	lampret	8657d 05h	/or1k/tags/stable_0_2_0_rc1
75	simgetstr added. eval_mem32 replaced with evalsim_mem32.	lampret	8657d 05h	/or1k/tags/stable_0_2_0_rc1
74	Same as DMMU.	lampret	8664d 04h	/or1k/tags/stable_0_2_0_rc1
73	Fixed all bugs. Now more or less works. IMMU still has some problems (exception start).	lampret	8664d 04h	/or1k/tags/stable_0_2_0_rc1
72	Added 'how to build GNU tools'	lampret	8669d 05h	/or1k/tags/stable_0_2_0_rc1
71	Clean two typos.	lampret	8674d 07h	/or1k/tags/stable_0_2_0_rc1
70	Basic setjmp/longjmp are ready.	lampret	8674d 07h	/or1k/tags/stable_0_2_0_rc1