OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] - Rev 1353

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1353 Modularise simulator command parsing nogj 7089d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim
1352 Optimise execution history tracking nogj 7089d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim
1351 Reindent create_watchpoints useing a more compact indentation style nogj 7089d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7089d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim
1347 Remove backup file nogj 7100d 17h /or1k/tags/stable_0_2_0_rc1/or1ksim
1346 Remove the global op structure nogj 7102d 09h /or1k/tags/stable_0_2_0_rc1/or1ksim
1345 Fix out-of-tree builds nogj 7102d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7102d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim
1343 * Fix warnings in insnset.c and execute.c nogj 7102d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.
nogj 7102d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim
1341 Mark wich operand is the destination operand in the architechture definition nogj 7102d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim
1338 l.ff1 instruction added andreje 7118d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim
1332 gcc 3.4.3 compile fix phoenix 7137d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim
1324 memory access functions fixes phoenix 7200d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim
1323 Adrian Wise: or1ksim bugfix & Solaris build phoenix 7201d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim
1321 some tests rely on exit(0) as a last std output text to pass phoenix 7204d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim
1320 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7206d 00h /or1k/tags/stable_0_2_0_rc1/or1ksim
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7206d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim
1316 added a warning phoenix 7223d 22h /or1k/tags/stable_0_2_0_rc1/or1ksim
1315 missing declaration when defined STACK_ARGS phoenix 7223d 22h /or1k/tags/stable_0_2_0_rc1/or1ksim

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.